1. Field of the Invention
The present invention relates to an array substrate and more particularly to an array substrate being capable of preventing damages on an active layer, and having an excellent property and high aperture ratio and a method of fabricating the array substrate.
2. Discussion of the Related Art
As the society has entered in earnest upon an information age, flat panel display devices, which have excellent capabilities of a thin profile, light weight and low power consumption, and so on, are introduced.
Among these devices, an active matrix type liquid crystal display (LCD) device is widely used for notebook computers, monitors, TV, and so on instead of a cathode ray tube (CRT), because of their high contrast ratio and characteristics adequate to display moving images.
On the other hand, an organic electroluminescent display (OELD) device is also widely used because their high brightness and low driving voltage. In addition, since the OELD device is a self-emission type, the OELD device produces high contrast ratio, a thin profile and a fast response time.
Both the LCD device and the OELD device require an array substrate where a thin film transistor (TFT) as a switching element in each pixel for controlling the pixel to be turned on and off. The OELD device additionally requires a driving TFT for driving an organic electroluminescent diode.
FIG. 1 is a cross-sectional view showing one pixel region of the related art array substrate. In FIG. 1, a gate electrode 15 is formed on a substrate 11 and in a driving region TrA, where a driving TFT Tr will be formed, inside a pixel region P. A gate line (not shown) connected to the gate electrode 15 is formed along a first direction. A gate insulating layer 18 is formed on the gate electrode 15 and the gate line. A semiconductor layer 28 including an active layer 22 of intrinsic amorphous silicon and an ohmic contact layer 26 of impurity-doped amorphous silicon is formed on the gate insulating layer 18 and in the driving region TrA. A source electrode 36 and a drain electrode 38 are formed on the semiconductor layer 28 and in the driving region TrA. The source electrode 36 is spaced apart from the drain electrode 38. A data line 33 connected to the source electrode 36 is formed along a second direction. The data line 33 crosses the gate line to define a pixel region P. The gate electrode 15, the gate insulating layer 18, the semiconductor layer 28, the source electrode 36 and the drain electrode 38 constitute the driving TFT Tr.
Although not shown, a switching TFT having substantially the same structure as the driving TFT Tr is formed in the pixel region P. The switching TFT is connected to the driving TFT Tr, the gate line and the data line 33.
A passivation layer 42 including a drain contact hole 45 is formed to cover the driving TFT Tr. On the passivation layer 42, a pixel electrode 50 connected to the drain electrode 38 through the drain contact hole 45 is formed. In FIG. 1, first and second patterns 27 and 23, which are respectively formed of the same material as the ohmic contact layer 26 and the active layer 22, are formed under the data line 33.
In the semiconductor layer 28 of the TFT Tr, the active layer 22 of intrinsic amorphous silicon has a difference in a thickness. Namely, the active layer 22 has a first thickness t1 at a central portion and a second thickness t2 at side portions. The first thickness t1 is different from the second thickness t2. Properties of the TFT Tr are degraded by the thickness difference in the active layer 22. The thickness difference in the active layer 22 results from a fabricating process explained with reference to FIG. 2.
FIG. 2 is a cross-sectional view illustrating a fabricating process of a semiconductor layer and source and drain electrode of the related art array substrate. For convenience of explanation, the gate electrode and the gate insulating layer under the active layer is not shown.
In FIG. 2, an intrinsic amorphous silicon layer (not shown), an impurity-doped amorphous silicon layer (not shown) and a metal layer (not shown) are sequentially formed on the substrate 11. Then, the metal layer, the impurity-doped amorphous silicon and the intrinsic amorphous silicon layer are patterned to form a metal pattern (not shown), an impurity-doped amorphous pattern (not shown) and an intrinsic amorphous silicon pattern (not shown).
Next, a center of the metal pattern is etched to form the source and drain electrodes 36 and 38 spaced apart from each other. As a result, a center of the impurity-doped amorphous silicon pattern is exposed through the source and drain electrodes 36 and 38.
A dry-etching process is performed onto the impurity-doped amorphous silicon pattern to removed the exposed impurity-doped amorphous silicon pattern using the source and drain electrodes 36 and 38 as an etching mask. As a result, the ohmic contact layer 26 is formed under the source and drain electrodes 36.
In this case, the dry-etching process is performed for a relative long time to completely remove the under the impurity-doped amorphous silicon pattern exposed through a space between the source and drain electrodes. As a result, a central portion of the active layer 22 under the removed impurity-doped amorphous silicon pattern is partially removed by the dry-etching process such that the active layer 22 has a difference in a thickness. (t1≠t2) If the dry-etching process is not performed for an enough long time, the impurity-doped amorphous silicon pattern partially remains on the active layer 22 such that properties of the TFT Tr (of FIG. 1) are seriously degraded. The thickness difference in the active layer 22 is an inevitable result of the above fabricating process for the array substrate.
In addition, since the active layer 22 is partially removed during the dry-etching process, the intrinsic amorphous silicon layer 20 for the active layer 22 should be formed to have an enough thickness above 1000 angstroms such that there are disadvantages in production costs and a fabricating time.
The TFT Tr is very important element for the array substrate. The TFT Tr is positioned in each pixel region and connected to the gate and data line such that a signal is selectively provided the pixel electrode in each pixel region through the TFT Tr. Unfortunately, since the active layer of the TFT Tr is formed of intrinsic amorphous silicon, there are some problems. For example, when light is irradiated onto the active layer or an electric field is applied to the active layer, the active layer is changed to be a metastable state such that there is a problem of a security of the TFT Tr. In addition, since mobility of carriers in a channel of the active layer is relatively low, the TFT Tr including the active layer of intrinsic amorphous silicon is not adequate to a driving element for the OELD device.
To resolve these problems, the TFT including an active layer of polycrystalline silicon, which is crystallized from intrinsic amorphous silicon by a crystallization process using a laser beam, is introduced. However, referring to FIG. 3, which is a cross-sectional view showing a TFT Tr including a semiconductor layer 55 of polycrystalline silicon for the related art array substrate, the semiconductor layer 55 includes a first region 55a and a second region 55b at both sides of the first region 55a. High concentration impurities should be doped into the second region 55b of the semiconductor layer 55. Accordingly, a doping process for the second region 55b and an implant apparatus for the doping process are required such that production costs are seriously increased. In addition, new process line is required.